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High-level test synthesis in Java Implementation Code 39 Extended in Java High-level test synthesis

High-level test synthesis generate, create none none for none projects code 39 barcode IN 2 R2 IN1 R1 IN 2 R2 IN 1 R1 IN 2 R2 SUB R3 R3 R4 R4 OUT R4 OUT OUT (a) (b) (c). Figure 15.21 (a) An RTL circuit, (b) its connectivity graph, and (c) its RT-scan graph R3(t) R1(t 1) R2(t none none 1) R4(t) R3(t 1). The vector that needs to be scanned is shown in the fourth row of Table 15.4.

To obtain R4 = 0011 in cycle 4, the above register assignments tell us that we need R3 = 0011 in cycle 3. This value in turn can be obtained with R1 = 0011 and R2 = 0000 in cycle 2. This implies that we must have IN 1 = 0011 and IN 2 = 0000 in cycle 1.

The other values in the table can be similarly obtained. The blank entries in the table correspond to don t-care values. The register assignment equations can also be used to propagate the captured fault effect to a primary output.

For example, if after applying the above combinational vector, the fault effect is captured in register R3, then it can be propagated to primary output register R4 in one clock cycle. It is possible that the fault being targeted interferes with the appropriate loading of the registers with the combinational vector or propagation of the error response to a primary output, leading to non-detection of the fault. However, in practice, this situation rarely occurs.

When the RT-scan graph has loops in it, it may be necessary to assume that some or all of the registers are directly resettable.. 15.4 RTL design for testability IN1 T s 1 T s2 T s 3 R3 R4 Figure 15.22 The RT-scan implementation Table 15.4. Derivation o f a test sequence for a combinational vector Cycle 1 2 3 4 R1 0011 0101 1110 R2 0000 0000 1010 R3 R4 IN 1 0011 0101 1110 0001 IN 2 0000 0000 1010 1111.

0011 0101. 15.4.3.2 Orthogonal scan We illustrate this metho none none d with the help of the RTL circuit shown in Figure 15.23(a). Its orthogonal scan implementation is shown in Figure 15.

23(b). As in the case of RTscan, the values are loaded into the registers in a direction orthogonal to the traditional scan path implementation, hence the name. For normal operation, test signal T is kept low.

If n is the datapath bit-width, then n AND gates are added at the right input of subtracter SUB. The select signals are modi ed in a manner similar to RT-scan. When T = 1, the following path is activated: IN 1 R1 SUB R2.

Note that when T = 1, all the bits at the right input of SUB are 0. The above path can be used to load registers R1 and R2 from primary input IN 1 with values corresponding to a test vector obtained through combinational test generation. After the test vector is applied.

High-level test synthesis IN 2 s1 R1 s2 R2 OUT MUL SUB (a) IN1 T s1 T s2 R1 IN 2 & R2 T Xn & OUT MUL SUB (b). Figure 15.23 (a) An RTL circuit, and (b) its orthogonal scan implementation to the circuit, the faul none for none t effect is captured in one of the registers. This effect can be propagated to the primary output OUT using the same path. This path can itself be tested beforehand by passing through it a string of 1s and 0s in the test mode.

In general, if a functional unit is used during orthogonal scan of the registers, then logic gates must be added to the bits of the input of the functional unit that is not on the scan path. This additional logic masks the input during scan. For an adder or subtracter, the AND gates, as shown in Figure 15.

23(b), make all the bits of that input 0. This enables the value at the other input to pass through unchanged. To pass a value through an input of a multiplier unchanged, the extra logic should make sure that the.

15.5 RTL built-in self-test multiplier s other input none for none has the value 0 01. Whenever possible, the orthogonal scan path should be chosen such that this extra logic is not on the critical path. Datapaths with many more functional units than registers may require multiple orthogonal scan paths to provide the desired logic values in all the registers.

It may also necessitate adding load signals to some registers in order to scan the registers in phases, one orthogonal scan con guration at a time. The load signals allow the values of those registers to be held while the registers are scanned in subsequent orthogonal scan con gurations. Multiple orthogonal scan con gurations also require more than one test signal.

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